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MITSUBISHI LSIs MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12 M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
DESCRIPTION
The MITSUBISHI M5M29FB/T800FP, VP, RV are 3.3V-only high speed 8,388,608-bit CMOS boot block Flash Memories suitable for mobile and personal computing, and communication products. The M5M29FB/T800FP, VP, RV are fabricated by CMOS technology for the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in 44pin SOP or 48pin TSOP(I).
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
FEATURES
................................. 524,288 word x 16bit ................................. 1,048,576 word x 8 bit ............................. VCC = 3.3V0.3V Supply voltage ................................ .............................. 80/100/120ns (Max) Access time
Organization Power Dissipation ....................... 108 mW (Max.) Read ....................... 144 mW (Max.) Program/Erase ....................... 0.72 mW (Max.) Standby Deep power down mode ....................... 3.3W (typ.) Auto program ....................... 7.5ms (typ.) Program Time ................................. 128word Program Unit Auto Erase ................................. 50 ms (typ.) Erase time Erase Unit Boot Block ................................. 8Kword / 16Kbyte x 1 ........................ 4Kword / 8Kbyte x 2 Parameter Block ....................... 16Kword / 32Kbyte x 1 Main Block ........................... 32Kword / 64Kbyte x 15 Program/Erase cycles ....................................... 100Kcycles Boot Block ........................... Bottom Boot M5M29FB800 ........................... Top Boot M5M29FT800 Other Functions Software Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Sleep Package 48-Lead, 12mmx 20mm TSOP (type-I) 44-Lead SOP
PIN CONFIGURATION (TOP VIEW)
ADDRESS INPUTS
CHIP ENABLE INPUT
NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 /CE GND /OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6
44 43 42 41 40 39
/RP
RESET/ POWER DOWN INPUT
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
/WE WRITE ENABLE INPUT A8 A9 A10 A11 ADDRESS A12 INPUTS A13 A14 A15 A16 /BYTE BYTE ENABLE INPUT GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
M5M29FB/T800FP
OUTPUT ENABLE INPUT
DATA INPUTS/ OUTPUTS
DATA INPUTS/ OUTPUTS
Outline 600mil 44-pin SOP (FP: 44P2A-A)
APPLICATION
Code Storage PC BIOS Digital Cellular Phone/Telecommunication
A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE /RP NC /WP RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38
M5M29FB/T800VP
37 36 35 34 33 32 31 30 29 28 27 26 25
A16 /BYTE GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 /OE GND /CE A0
A16 /BYTE GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 /OE GND /CE A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38
M5M29FB/T800RV
37 36 35 34 33 32 31 30 29 28 27 26 25
A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE /RP NC /WP RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1
Outline 48pin TSOP type-I (12 X 20mm) VP(Normal bend): 48P3R-B
RV(Reverse bend): 48P3R-C
NC : NO CONNECTION
This product is compatible with HN29WB/T800 by Hitachi Ltd. 1
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK DIAGRAM
A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
/CE /OE /WE /WP /RP /BYTE RY/BY
128 WORD PAGE BUFFER Boot Block Parameter Block1 Parameter Block2 Main Block Main Block 8KW 4KW 4KW 16KW 32KW
VCC (3.3V) GND (0V)
X-DECODER
ADDRESS INPUTS
Main Block
32KW
Y-DECODER
Y-GATE / SENSE AMP.
STATUS / ID REGISTER
MULTIPLEXER
CHIP ENABLE INPUT OUTPUT ENABLE INPUT WRITE ENABLE INPUT WRITE PROTECT INPUT RESET/POWER DOWN INPUT BYTE ENABLE INPUT READY/BUSY OUTPUT
CUI
WSM INPUT/OUTPUT BUFFERS
D15/A-1D14D13D12
D3 D2 D1 D0
DATA INPUTS/OUTPUTS
FUNCTION
The M5M29FB/T800FP,VP,RV includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Powerdown mode is enabled when the /RP pin is at GND, minimizing power consumption. Read The M5M29FB/T800FP,VP,RV has three read modes, which accesses to the memory array, the Device Identifier and the Status Register. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the M5M29FB/T800 automatically resets to read array mode. In the read array mode, low level input to /CE and /OE, high level input to /WE and /RP, and address signals to the address inputs (A0-A18) output the data of the addressed location to the data input/output(D0-15). Write Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They also enable block erase and program. The CUI is written by bringing /WE to low level, while /CE is at low level and /OE is at high level. Address and data are latched on the earlier rising edge of /WE and /CE. Standard micro-processor write timings are used. Output Disable When /OE is at VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. Standby When /CE is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-impedance(High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. Deep Power-Down When /RP is at VIL, the device is in the deep powerdown mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance(High-Z) state. After return from powerdown, the CUI is reset to Read Array , and the Status Register is cleared to value 80H. During block erase or program modes, /RP low will abort either operation. Memory array data of the block being altered become invalid.
2
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITIONS The device operations are selected by writing specific software command into the Command User Interface. Read Array Command (FFH) The device is in Read Array mode on initial device powerup and after exit from deep powerdown, or by writing FFH to the Command User Interface. The device remains in Read Array mode until the other commands are written. Read Device Identifier Command (90H) Though PROM programmers can normally read device identifier codes by raising A9 to VID, multiplexing high voltage onto address lines is not desired for micro-processor system. It is an other means to read device identifier codes that Read Device Identifier Code Command(90H) is written to the command latch. Following the command write, the manufacturer code and the device code can be read from address 0000H and 0001H, respectively. Read Status Register Command (70H) The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. The contents of Status Register are latched on the later falling edge of /OE or /CE. So /CE or /OE must be toggled every status read. Clear Status Register Command (50H) The Erase Status and Program Status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions. Block Erase / Confirm Command (20H/D0H) Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Page Program Commands(41H) Page Program allows fast programming of 128words of data. Writing of 41H initiates the page program operation. From 2nd cycle to 129th cycle write data must be serially inputted. Address A6-0 have to be incremented from 00H to 7FH. After completion of data loading, the WSM controls the program pulse application and verify operation. Basically re-program must not be done on a page which has already programmed. Suspend/Resume Command (B0H/D0H) Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes. DATA PROTECTION The M5M29FB/T800 provides selectable block locking of memory blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the M5M29FB/T800 has a master Write Protect pin (WP) which prevents any modifications to memory blocks whose lock-bits are set to "0", when /WP is low. When /WP is high or /RP is VHH, all blocks can be programmed or erased regardless of the state of the lock-bits, and the lock-bits are cleared to "1" by erase. Power Supply Voltage When the power supply voltage (Vcc) is less than 2.2V, the device is set to the Read-only mode. A delay time of 2 us is required before any device operation is initiated. The delay time is measured from the time Vcc reaches Vccmin (3.0V). During power up, /RP=GND is recommended. Falling in Busy status is not recommended for possibility of damaging the device.
3
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
x8 ( Bytemode) x16 ( Wordmode) x8 ( Bytemode) x16 ( Wordmode)
F0000H-FFFFFH 78000H-7FFFFH E0000H-EFFFFH 70000H-77FFFH D0000H-DFFFFH 68000H-6FFFFH C0000H-CFFFFH 60000H-67FFFH B0000H-BFFFFH 58000H-5FFFFH A0000H-AFFFFH 50000H-57FFFH 90000H-9FFFFH 48000H-4FFFFH 80000H-8FFFFH 40000H-47FFFH 70000H-7FFFFH 38000H-3FFFFH 60000H-6FFFFH 30000H-37FFFH 50000H-5FFFFH 28000H-2FFFFH 40000H-4FFFFH 20000H-27FFFH 30000H-3FFFFH 18000H-1FFFFH 20000H-2FFFFH 10000H-17FFFH 10000H-1FFFFH 08000H-0FFFFH 08000H-0FFFFH 04000H-07FFFH 06000H-07FFFH 03000H-03FFFH 04000H-05FFFH 02000H-02FFFH 00000H-03FFFH 00000H-01FFFH A-1-A18(Bytemode) A0-A18(Wordmode)
32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 16Kword MAIN BLOCK 4Kword PARAMETER BLOCK 4Kword PARAMETER BLOCK 8Kword BOOT BLOCK
M5M29FB800 Memory Map
FC000H-FFFFFH 7E000H-7FFFFH FA000H-FBFFFH 7D000H-7DFFFH F8000H-F9FFFH 7C000H-7CFFFH F0000H-F7FFFH 78000H-7BFFFH E0000H-EFFFFH 70000H-77FFFH D0000H-DFFFFH 68000H-6FFFFH C0000H-CFFFFH 60000H-67FFFH B0000H-BFFFFH 58000H-5FFFFH A0000H-AFFFFH 50000H-57FFFH 90000H-9FFFFH 48000H-4FFFFH 80000H-8FFFFH 40000H-47FFFH 70000H-7FFFFH 38000H-3FFFFH 60000H-6FFFFH 30000H-37FFFH 50000H-5FFFFH 28000H-2FFFFH 40000H-4FFFFH 20000H-27FFFH 30000H-3FFFFH 18000H-1FFFFH 20000H-2FFFFH 10000H-17FFFH 10000H-1FFFFH 08000H-0FFFFH 00000H-0FFFFH 00000H-07FFFH A-1-A18(Bytemode) A0-A18(Wordmode)
8Kword BOOT BLOCK 4Kword PARAMETER BLOCK 4Kword PARAMETER BLOCK 16Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK
M5M29FT800 Memory Map
BUS OPERATIONS Bus Operations for Word-Wide Mode (/BYTE=VIH)
Mode Read Pins /CE VIL VIL VIL VIL VIL VIH VIL VIL VIL X /OE VIL VIL VIL VIL VIH X 2) VIH VIH VIH X /WE VIH VIH VIH VIH VIH X VIL VIL VIL X /RP VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL DQ0-15 Data out Status Register Data Lock Bit Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data in Command Command Hi-Z RY/BY VOH (Hi-Z) X 1) X VOH (Hi-Z) X X X X X VOH (Hi-Z)
Array Status Register Lock Bit Status Identifier Code Output disable Stand by Program Write Erase Others Deep Power Down
Bus Operations for Byte-Wide Mode (BYTE=VIL)
Mode Pins /CE VIL VIL VIL VIL VIL VIH VIL VIL VIL X /OE VIL VIL VIL VIL VIH X 2) VIH VIH VIH X /WE VIH VIH VIH VIH VIH X VIL VIL VIL X /RP VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL DQ0-7 Data out Status Register Data Lock Bit Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data in Command Command Hi-Z RY/BY VOH (Hi-Z) X 1) X VOH (Hi-Z) X X X X X VOH (Hi-Z)
Array Read Status Register Lock Bit Status Identifier Code Output disable Stand by Program Write Erase Others Deep Power Down
1) X at RY/BY is VOL or VOH(Hi-Z). *The RY/BY is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY signal to transition high indicating a Ready WSM condition. 2) X can be VIH or VIL for control pins.
4
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY SOFTWARE COMMAND DEFINITION Command List
Command Read Array Device Identifier Read Status Register Clear Status Register Page Program 4) Block Erase / Confirm Suspend Resume Read Lock Bit Status Lock Bit Program / Confirm Erase All Unlocked Blocks Sleep 7) Mode Write Write Write Write Write Write Write Write Write Write Write Write 1st bus cycle Address Data (D7-0) X X X X X X X X X X X X FFH 90H 70H 50H 41H 20H B0H D0H 71H 77H A7H F0H Mode 2nd bus cycle Address Data (D7-0) IA 2) X WA0 4) BA 5) ID 2) SRD 3) WD0 4) D0H Write WA1 WD1 Mode 3rd bus cycle Address Data (D7-0)
Read Read Write Write
Read Write Write
BA BA X
DQ6 6) D0H D0H
1) In the word-wide mode, upper byte data (D8-D15) is ignored. 2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code, /BYTE =VIL : A-1, A1-A18 = VIL, /BYTE =VIH : A1-A18 = VIL 3) SRD = Status Register Data 4) WA=Write Address, WD=Write Data. /BYTE =VIL : Write Address and Write Data must be provided sequentially from 00H to FFH for A-1-A6. Page size is 256Byte (256byte x 8bit), /BYTE =VIH : Write Address and Write Data must be provided sequentially from 00H to 7FH for A0-A6. Page size is 128word (128word x 16bit). 5) BA = Block Address ( Addresses except Block Address mest be VIH.) 6) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked. 7) Sleep command (F0H) put the device into the sleep mode after completing the current operation. The active current is reduced to deep power -down levels. The Read Array command (FFH) must be written to get the device out of sleep mode.
BLOCK LOCKING
SOP Package TSOP Package
/RP VIL VHH VIH VIH
Lock Bit(Internally) X X 0 1
/RP VIL VHH VIH VIH VIH
/WP X X VIL VIL VIH
Lock Bit(Internally) X X 0 1 X
Write Protection Provided All Blocks Locked (Deep Power Down Mode) All Blocks UnLocked Blocks Locked (Depend on Lock Bit Data) Blocks Unlocked (Depend on Lock Bit Data) All Blocks Unlocked
D6 provides Lock Status of each block after writing the Read Lock Status command (71H). In case of TSOP package, /WP pin must not be switched during performing Read / Write operations or WSM Busy (WSMS = 0).
STATUS REGISTER
Symbol SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 (D7) (D6) (D5) (D4) (D3) (D2) (D1) (D0) Status Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program Reserved Reserved Device Sleep Status Definition "1" Ready Suspended Error Error Error Device in Sleep "0" Busy Operation in Progress / Completed Successful Successful Successful Device Not in Sleep
*The RY/BY is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY signal to transition high indicating a Ready WSM condition. *D3 indicates the block status after the page programming. When D3 is "1", the page has the over-programed cell . If over-program occures, the device is block fail. However if D3 is "1", please try the block erase to the block. The block may revive.
DEVICE IDENTIFIER CODE
Code Manufacturer Code Device Code (-T) Device Code (-B) Pins A0 VIL VIH VIH D7 0 0 0 D6 0 1 1 D5 0 0 0 D4 1 1 1 D3 1 1 1 D2 1 1 1 D1 0 0 1 D0 0 1 0 Hex. Data 1CH 5DH 5EH
In the word-wide mode, the same data as D7-0 is read out from D15-8. A9 = VHH Mode : A9 = 11.5V~13.0V Set A9 to VHH min.200ns before falling edge of /CE in ready status. Min.200ns after return to VIH ,device can't be accessed. A1~A8, A10~A18, /CE,/OE = VIL, /WE = VIH D15/A-1 = VIL (/BYTE = L)
5
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI1 VI2 Ta Tbs Tstg I OUT Parameter Vcc voltage All input or output voltage except Vcc,A9,/RP1) A9,RP supply voltage Ambient temperature Temperature under bias Storage temperature Output short circuit current Conditions
With respect to Ground
Min -0.2 -0.6 -0.6 0 -10 -65
Max 4.6 4.6 14.0 70 80 125 100
Unit V V V C C C mA
1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is VCC+0.5V which, during transitions, may overshoot to VCC+1.5V for periods <20ns.
CAPACITANCE
Symbol CIN COUT Parameter Input capacitance (Address, Control Pins) Output capacitance Test conditions Ta = 25C, f = 1MHz, Vin = Vout = 0V Min Limits Typ Max 8 12 Unit pF pF
DC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70C, Vcc = 3.3V0.3V, unless otherwise noted)
Symbol ILI ILO ISB1 ISB2 ISB3 ISB4 ICC1 ICC2 ICC3 ICC4 ICC5 I RP IID VIHH VID VIL VIH VOL VOH1 VOH2 VLKO Parameter Input leakage current Output leakage current VCC standby current Test conditions 0VVINVCC 0VVOUTVCC VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH VCC = 3.6V, VIN=GND or VCC, /CE = /RP = /WP= VCC0.3V VCC = 3.6V, VIN=VIL/VIH, /RP = VIL VCC = 3.6V, VIN=GND or VCC, /RP =GND0.3V VCC = 3.6V, VIN=VIL/VIH, /CE = VIL, /RP=OE=VIH, f = 10MHz, IOUT = 0mA VCC = 3.6V,VIN=VIL/VIH, /CE =/WE= VIL, /RP=/OE=VIH VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH /RP = VHH max A9 = VID max 11.4 11.4 - 0.5 2.0 IOL = 5.8mA IOH = -2.5mA IOH = -100A 0.85Vcc
Vcc-0.4
Min
Limits Typ1)
50 1 5 1 7
Max 1.0 10 200 5 15 5 25 30 40 40 200 100 100 12.6 12.6 0.8
Vcc+0.5
Unit A A A A A A mA mA mA mA A A A V V V V V V V V
VCC deep powerdown current VCC read current for Word or Byte VCC Write current for Word or Byte VCC program current VCC erase current VCC suspend current /RP all block unlock current A9 intelligent identifier current /RP unlock voltage A9 intelligent identifier voltage Input low voltage Input high voltage Output low voltage Output high voltage Low VCC Lock-Out voltage 2)
12.0 12.0
0.45
1.5
2.5
All currents are in RMS unless otherwise noted. 1) Typical values at Vcc=3.3V, Ta=25C 2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO. If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents
may occur.
6
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC ELECTRICAL CHARACTERISTICS (Ta = 0 ~70C, Vcc = 3.30.3V) Read-Only Mode
Symbol
Parameter Read cycle time Address access time Chip enable access time Output enable access time Chip enable to output in low-Z Chip enable high to output in high Z Output enable to output in low-Z Output enable high to output in high Z /RP low to output high-Z /BYTE access time /BYTE low to output high-Z Output hold from /CE, /OE, addresses /CE low to /BYTE high or low Address to /BYTE high or low /OE hold from /WE high /RP recovery to /CE low
tRC ta (AD) ta (CE) ta (OE) tCLZ tDF(CE) tOLZ tDF(OE) tPHZ tBHZ tOH tBCD tBAD tOEH tPS
tAVAV tAVQV tELQV tGLQV tELQX tEHQZ tGLQX tGHQZ tPLQZ tFLQZ tOH tELFL/H tAVFL/H tWHGL tPHEL
M5M29FB/T800-80 Min Typ Max 80 80 80 40 0 25 0 25 150 80 25 0 5 5 80 500
Limits M5M29FB/T800-10 Min Typ Max 100 100 100 50 0 25 0 25 150 100 25 0 5 5 100 500
M5M29FB/T800-12 Min Typ Max 120 120 120 60 0 30 0 30 300 120 30 0 5 5 120 500
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ta(BYTE) tFL/HQV
Timing measurements are made under AC waveforms for read operations.
AC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70C, Vcc = 3.3V0.3V) Write Mode (/WE control)
Symbol
Parameter Write cycle time Address set-up time Address hold time Data set-up time Data hold time Chip enable set-up time Chip enable hold time Write pulse width Write pulse width high Byte enable high or low set-up time Byte enable high or low hold time Block Lock set-up to write enable high Block Lockhold from valid SRD Duration of auto-program operation Duration of auto-block erase operation Write enable high to RY/BY low /RP high recovery to write enable low
tWC tAS tAH tDS tDH tCS tCH tWP tWPH tBS tBH tBLS tWPS tBLH tWPH tDAP tDAE tWHRL tPS
tAVAV tAVWH tWHAX tDVWH tWHDX tELWL tWHEH tWLWH tWHWL tFL/HWH tWHFL/H tPHHWH tQVPH tWHRH1 tWHRH2 tWHRL tPHWL
M5M29FB/T800-80 Min Typ Max 80 50 10 50 10 0 0 60 20 50 80 80 0 7.5 50 500 120 600 80
Limits M5M29FB/T800-10 Min Typ Max 100 50 10 50 10 0 0 60 20 50 100 100 0 7.5 50 500 120 600 100
M5M29FB/T800-12 Min Typ Max 120 50 10 50 10 0 0 60 20 50 120 120 0 7.5 50 500 120 600 120
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns
Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at Vcc=3.3V, Ta=25C
7
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70C, Vcc = 3.3V0.3V) Write Mode (/CE control)
Symbol
Parameter Write cycle time Address set-up time Address hold time Data set-up time Data hold time Write enable set-up time Write enable hold time /CE pulse width /CE pulse width high Byte enable high or low set-up time Byte enable high or low hold time Block Lock set-up to write enable high Block Lockhold from valid SRD Duration of auto-program operation Duration of auto-block erase operation /CE enable high to RY/BY low /RP high recovery to write enable low
tWC tAS tAH tDS tDH tWS tWH tCEP tCEPH tBS tBH tBLS tWPS tBLH tWPH tDAP tDAE tEHRL tPS
tAVAV tAVEH tEHAX tDVEH tEHDX tWLEL tEHWH tELEH tEHEL tFL/HEH tEHFL/H tPHHEH tQVPH tEHRH1 tEHRH2 tEHRL tPHEL
M5M29FB/T800-80 Min Typ Max 80 50 10 50 10 0 0 60 20 50 80 80 0 7.5 50 500 120 600 80
Limits M5M29FB/T800-10 Min Typ Max 100 50 10 50 10 0 0 60 20 50 100 100 0 7.5 50 500 120 600 100
M5M29FB/T800-12 Min Typ Max 120 50 10 50 10 0 0 60 20 50 120 120 0 7.5 50 500 120 600 120
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns
Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at Vcc=3.3V, Ta=25C
Erase and Program Performance
Parameter Block Erase Time Main Block Write Time (Page Mode) Page Write Time Min Typ 50 1.9 7.5 Max 600 3.8 120 Unit ms sec ms
Vcc Power Up / Down Timing
Symbol tVCS Parameter /RP =VIH set-up time from Vccmin Min 2 Typ Max Unit s
During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. The device must be protected against initiation of write cycle for memory contens during power up/down. The delay time of min.2sec is always required before read operation or write operation is initiated from the time Vcc reaches Vccmin during power up/down. By holding /RP VIL, the contens of memory is protected during Vcc power up/down. During power up, /RP must be held VIL for min.2s from the time Vcc reaches Vccmin. During power down, /RP must be held VIL until Vcc reaches GND. /RP doesn't have latch mode ,so /RP must be held VIH during read operation or erase/program operation.
8
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY Vcc POWER UP / DOWN TIMING
Read /Write Inhibit Read /Write Inhibit Read /Write Inhibit
VCC
3.3V GND tVCS VIH VIL VIH VIL
/RP
/CE
tPS
tPS
/WE
VIH VIL
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
ADDRESSES
VIH VIL
ADDRESS VALID
TEST CONDITIONS FOR AC CHARACTERISTICS Input voltage : VIL = 0V, VIH = 3.0V Input rise and fall times : 5ns (80ns) 10ns (100/120ns) Reference voltage at timing measurement : 1.5V Output load : 1TTL gate + CL(100pF for 100/120ns) CL(30pF for 80ns) or HIGH-Z
1.3V 1N914 3.3k DUT CL =30/100pF
tRC ta (AD) ta (CE) tDF(CE)
/CE
VIH VIL
/OE
VIH VIL tOEH ta (OE) tOLZ HIGH-Z tPS tCLZ tDF(OE) tOH
/WE
VIH VIL
DATA
VOH VOL
OUTPUT VALID
/RP
VIH VIL
tPHZ
BYTE AC WAVEFORMS FOR READ OPERATION
ADDRESSES VIH (A0 - A18) VIL VIH VIL ta(CE) /OE VIH VIL ta(OE) ta(BYTE) tOLZ tCLZ tBCD HIGH-Z tBAD
OUTPUT VALID VALID VALID ADDRESS VALID ADDRESS VALID
ta(AD) /CE
tDF(CE)
tDF(OE) tBAD ta(BYTE)
/BYTE
VIH VIL
tOH
DATA (D0 - D7) VIL DATA (D8 - D14) VIL VIH VIL VIH
VIH
tBHZ HIGH-Z
VALID
ta(AD)
D15 / A-1
A-1
D15
A-1
When /BYTE=VIH, /CE=/OE=VIL , D15/A-1 is output status. At this time, input signal must not be applied.
9
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR PAGE PROGRAM OPERATION (/WE control)
VIH A7~A18 VIL
/BYTE=VIL ADDRESS VALID 00H 00H 01H 01H 02H~FEH 02H~7EH FFH 7FH
PROGRAM READ STATUS WRITE READ REGISTER ARRAY COMMAND
(A-1~A6) VIH
/BYTE=VIH VIL
(A0 ~A6) /CE /OE VIH VIL tCS VIH VIL /WE VIH VIL DATA VIH VIL RY/BY VOH VOL /BYTE VIH VIL VHH /RP VIH VIL /WP VIH VIL
tWC
tAS tCH
tAH ta(CE) ta(OE) tOEH tDAE,tDAP tDH
DIN DIN DIN DIN SRD FFH
tWPH
tWP
41H
tDS
tWHRL
tBS
tBH
tBLS tPS
tBLH
tWPS
tWPH
AC WAVEFORMS FOR ERASE OPERATIONS (/WE control)
VIH
ADDRESSES
ERASE READ STATUS REGISTER WRITE READ ARRAY COMMAND
VIL tWC VIH /CE VIL tCS VIH /OE VIL VIH /WE VIL tWP VIH DATA
20H
ADDRESS VALID
tAS
tAH
ta(CE)
tCH tOEH tDAP,tDAE tDH
D0H
ta(OE)
tWPH
tDS
SRD
FFH
VIL VOH VOL tBS VIH
tWHRL
RY/BY
tBH
/BYTE
VIL tBLS VHH tPS tWPS VIH VIL VIH
tBLH
/RP
tWPH
/WP
VIL
May 1997 , Rev.6.1
10
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR PAGE PROGRAM OPERATION (/CE control)
VIH A7~A18 VIL
/BYTE=VIL 00H 00H ADDRESS VALID 01H 01H 02H~FEH 02H~7EH FFH 7FH
PROGRAM
READ STATUS WRITE READ REGISTER ARRAY COMMAND
(A-1~A6)VIH
/BYTE=VIH VIL
(A0 ~A6) /CE /OE VIH VIL VIH VIL /WE VIH VIL DATA VIH VIL RY/BY VOH VOL /BYTE VIH VIL VHH /RP VIH VIL VIH VIL
tWC tCEPH tCEP tWS tWH
tAS
tAH ta(CE) ta(OE) tOEH tDAE,tDAP tDH
DIN DIN DIN DIN SRD FFH
tDS
41H
tEHRL
tBS
tBH
tBLS tPS
tBLH
tWPS
tWPH
/WP
AC WAVEFORMS FOR ERASE OPERATIONS (/CE control)
ERASE
ADDRESSES
VIH VIL tWC VIH
ADDRESS VALID
READ STATUS REGISTER
WRITE READ ARRAY COMMAND
tAS
tAH
ta(CE)
/CE
VIL tCEP VIH tCEPH tOEH tDAP,tDAE tDH
D0H SRD FFH
ta(OE)
/OE
VIL tWS VIH tWH tDS
20H
/WE
VIL VIH
DATA
VIL VOH VOL tBS VIH
tEHRL
RY/BY
tBH
/BYTE VIL tBLS VHH /RP VIH VIL VIH /WP VIL
May 1997 , Rev.6.1
tBLH
tPS tWPS tWPH
11
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
FULL STATUS CHECK PROCEDURE
STATUS REGISTER READ
SR.4 =1 and SR.5 =1 ? NO
YES
COMMAND SEQUENCE ERROR
SR.5 = 0 ? NO YES
BLOCK ERASE ERROR
SR.4 = 0 ? NO YES
PROGRAM ERROR (PAGE, LOCK BIT)
SR.3 = 0 ? NO YES SUCCESSFUL (BLOCK ERASE, PROGRAM)
PROGRAM ERROR (BLOCK)
LOCK BIT PROGRAM FLOW CHART
START
PAGE PROGRAM FLOW CHART
START
WRITE 77H
WRITE 41H
WRITE D0H BLOCK ADDRESS
n=0
SR.7 = 1 ? NO YES
WRITE ADDRESS n, DATA n
n = n+1
SR.4 = 0 ? NO YES LOCK BIT PROGRAM SUCCESSFUL
LOCK BIT PROGRAM FAILED
n = FFH ? or n = 7FH ? YES
NO
STATUS REGISTER READ
SR.7 = 1 ?
NO
WRITE B0H ?
NO
YES FULL STATUS CHECK IF DESIRED
YES
SUSPEND LOOP WRITE D0H
YES
PAGE PROGRAM COMPLETED
12
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK ERASE FLOW CHART
START
SUSPEND / RESUME FLOW CHART
START
WRITE 20H
WRITE B0H
SUSPEND
WRITE D0H BLOCK ADDRESS
STATUS REGISTER READ
STATUS REGISTER READ
SR.7 = 1? NO YES
NO SR.7 = 1 ?
WRITE B0H ?
NO
SR.6 =1? YES WRITE FFH
NO
PROGRAM / ERASE COMPLETED
YES FULL STATUS CHECK IF DESIRED
YES
SUSPEND LOOP WRITE D0H
YES DONE READING ? YES WRITE D0H READ ARRAY DATA
BLOCK ERASE COMPLETED
NO
RESUME
OPERATION RESUMED
13
May 1997 , Rev.6.1
14 Read/Standby State
70H 71H 70H 90H 71H 71H FFH FFH 50H 90H 70H
Read Status Register Read Device Identifier Read Lock Status
90H FFH
50H
Clear Status Register
Sleep State
71H
Read Device Identifier Read Lock Status
71H 70H
FFH [Wake Up / R
90H
70H
90H
ead Arr ay]
Read Status Register
F0H [Sleep] 41H 77H FFH FFH 20H A7H FFH
Read Array
Setup State Page Program Setup
OTHER WDi i=0-255 D0H D0H
Lock Bit Program Setup
Block Erase Setup
Erase All Unlocked Blocks Setup
OTHER D0H OTHER
OPERATION STATUS and EFFECTIVE COMMAND
Internal State
F0H
Program & Verify Read Status Register
D0H B0H B0H READY D0H
Erase & Verify Read Status Register
request Sleep
return
IS REQUEST SLEEP? Y N
Suspend State Read Status Register
90H 70H 90H 90H 90H FFH FFH FFH 70H 71H 70H F0H 71H invalid data
Read Device Identifier
Read Lock Status
71H
request Sleep
return
M5M29FB/T800FP,VP,RV-80,-10,-12
MITSUBISHI LSIs
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
May 1997 , Rev.6.1
Read Array

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